CVLD101 - DIGITAL LOGIC AND COMPUTER  DESIGN (80 periods)

Number systems, Boolean algebra, K-map two, four variables, logic gates, combinational logic, combinational logic with MSI and LSI.

Sequential logic – flip flops, triggering of flip flops, Registers – shift registers, Counters – ripple counter, synchronous counter, Memory – RAM, ROM. etc,

Processor logic design – design of arithmetic logic unit, design

shift register Advanced Digital Designs – pipe line processing  

PLDs, FPGA, ASIC: Introduction to PLDs, ROMS, Logic Array  (PLA)

Programmable array logic, placement and routing, introduction to asic-types, design flow.

CVLD102 - VLSI DESIGN WITH VERILOG (80 periods)

Design method lies, ports, Language elements, Lexical Conventions, Data types, Memories, Arrays, Tri-state, Operands, Operators, Operator precedence.

Assignments - Continuous Assignment, Delays, Procedural Assignments, Procedural Continuous Assignments, Assign Design, Gate level modeling,  Gate Types, Gate Delays, User Defined Primitives (UDPs), definition, Rules, state tables, Combinational UDPs, Sequential UDPs, Mixing level sensitive and edge-sensitive descriptions, instantiating UDP primitives.

Behavioral modeling- structured procedures, procedural assignments, procedural timing controls, block statements, continuous assignments Vs procedural assignments, conditional statements, multi-way decision statements, looping statements, task and functions- Distinctions between tasks and function, tasks, functions, Switch Level Modeling – Switch modeling elements, bi-directional switches, power and ground, Resistive switches.

Useful modeling techniques – Bi-directional ports, hierarchical path name, overringding parameters, named blocks, system tasks functions, simulation time, tracing, compiler directives, Finite State Machine – Sequential current state register, combinational next state logic, combinational output logic, basic structure of a Moore machine, basic structure of a mealy machine, state machine encoding.