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    Advanced Computing & Information Processing

PG Diploma VLSI Design

General Information

Subject of Study

Syllabus:

PGDV101 - DIGITAL LOGIC AND COMPUTER  DESIGN (80 periods)

Number systems, Boolean algebra, K-map two, four variables, logic gates, combinational logic, combinational logic with MSI and LSI.  

Sequential logic – flip flops, triggering of flip flops, Registers – shift registers, Counters – ripple counter, synchronous counter, Memory – RAM, ROM. etc,  

Processor logic design – design of arithmetic logic unit, design 

shift register Advanced Digital Designs – pipe line processing  

PGDV102 - VLSI DESIGN WITH VERILOG (80 periods)

Design method lies, ports, Language elements, Lexical Conventions, Data types, Memories, Arrays, Tri-state, Operands, Operators, Operator precedence.

Assignments - Continuous Assignment, Delays, Procedural Assignments, Procedural Continuous Assignments, Assign Design, Gate level modeling,  Gate Types, Gate Delays, User Defined Primitives (UDPs), definition, Rules, state tables, Combinational UDPs, Sequential UDPs, Mixing level sensitive and edge-sensitive descriptions, instantiating UDP primitives.

Behavioral modeling- structured procedures, procedural assignments, procedural timing controls, block statements, continuous assignments Vs procedural assignments, conditional statements, multi-way decision statements, looping statements, task and functions- Distinctions between tasks and function, tasks, functions, Switch Level Modeling – Switch modeling elements, bi-directional switches, power and ground, Resistive switches

Useful modeling techniques – Bi-directional ports, hierarchical path name, overringding parameters, named blocks, system tasks functions, simulation time, tracing, compiler directives, Finite State Machine – Sequential current state register, combinational next state logic, combinational output logic, basic structure of a Moore machine, basic structure of a mealy machine, state machine encoding.  

PGDV103 - VLSI DESIGN WITH HDL (80 periods)

Introduction, basic terminology, entity declaration, architecture body, configuration declaration, package declaration, package body, model analysis, identifiers, data objects, data types, operators.

Behavioral Modeling – entity declaration, architecture body, process statement, variable, signal assignment, statements - wait, if, case, null, loop next, assertion, report, multiple process, Data modeling – concurrent signal assignment, delta delay, multiple drivers, block statements, Structural Modeling – component declaration, component instantiation.

Generic, Configurations specification, declaration, conversion functions, direct instantiation, Subprograms, Subprograms overloading, operator overloading, signatures, Package declaration, package body, design file, design libraries

Advanced features – Entity statement, generate statement, aliases, type conversions, guarded signals, attributes, Model simulation – writing test bench, Hardware modeling – modeling entity interface, simple elements, regular structure, delays, conditional operations, synchronous logic, state machine.

PGDV104 - LIST OF EXPERIMENTS USING VHDL  

Simple Design exercises:

1. Half adder, Full adder, Subtractor Flip Flops, 4bit comparator

2. Parity generator

3. Bit up/down counter with load able count  

4. Decoder and encoder  

5. 8 bit shift register

6. 8:1 multiplexer

7. Flip-Flop –RS,D,T,JK

8. Barrel shifter

9. N by m binary multiplier

10. Code Converter-BCD to Seven segment, BCD to Excess3.  

PGDV105 - PLDs, FPGAs (80 periods)

Introduction to PLDs : ROMs, Logic array (PLA), Programmable array logic, GAL,  bipolar PLA, NMOS PLA, PAL 14L 4, examples 

Programmable gate arrays :  Xilinx logic cell array (LCA) – I/O Block – Programmable interconnect – Xilinx – 3000 series and 4000 series FPGAs.Altera CPLDs, altera FLEX 10 K series PLDs.

Placement and routing : Mincut based placement – iterative improvement placement– Routing: Segmented channel routing – Maze routing – Routability and routing resources – Net delays    

PGDV106 - ASIC (80 periods)  

Introduction to ASICs : Types of ASICs, design flow, economics of ASICs   Comparison between ASIC technologies: Product cost, ASIC fixed and variable costs, ASIC cell libraries – An overview of programmable ASICs : Programming technologies – Practical issues – FPGA economics – Programmable ASIC logic cells:  Actel, Xilinx and Altera family of programmable ASICs

Programmable ASIC interconnect : Actel ACT: Routing resources - Elmore’s constant - RC delay –  Antifuse parasitic capacitance – ACT2 and ACT3.  Xilinx LCA,  EPLD,  Altera MAX 5000, 7000 and 9000 – Altera FLEX – Synthesis of Half gate ASIC using these families and comparison – ASIC construction – Physical design – CAD tools – System partitioning – Estimating ASIC size – Power dissipation – FPGA partitioning – Partitioning methods

Floor planning : Goals and objectives – Measurement of delay – Floor planning tools – Channel definition – I/O and power planning – Clock planning placement – Physical design flow – Information formats.                 

PGDV107 - CMOS DESIGNS (80 periods)  

Introduction to CMOS circuits : MOS transistors, MOS switches, CMOS logic: Inverter, combinational logic, NAND, NOR gates, compound gates, Multiplexes. Memory: Latches and registers. 

MOS transistor theory : NMOS, PMOS enhancement mode transistors, Threshold voltage, body effect, CMOS inverter DC characteristics  

CMOS processing technology : wafer processing, oxidation, epitaxy, deposition, lon implantation, diffusion, latch up, Si gate process.  

CMOS Technology and physical design : Basic CMOS technology, p well, n well, twin tub, silicon on insulator, Bi CMOS, basic physical design of simple logic gates, inverter, NAND, NOR.

PGDV108   LIST OF EXPERIMENTS USING Verilog  

1. Simple Design exercises: 

2. Half adder, Full adder, Subtractor Flip Flops, 4bit comparator

3. Parity generator

4. Bit up/down counter with load able count

5. Decoder and encoder  

6. 8 bit shift register  

7. 8:1 multiplexer  

8. Flip-Flop –RS, D, T, JK  

9. Barrel shifter

10. N by m binary multiplier  

11. Code Converter-BCD to Seven segment, BCD to Excess3

Tools : Xilinx, Cadence, Model SIM, Leonardo Spectrum Tools

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