TIFAC - CORE AT SASTRA UNIVERSITY
Advanced Computing & Information Processing
National Seminar on System on Chip (NSSOC - 2003)
27th Nov. to 29th Nov 2003 - A Report
three-day national seminar on System-On-Chip was organized by
TIFAC-CORE, SASTRA in association with Ministry of Information
Technology, Govt. of India and IEEE India (Electron Devices
Society / Microwave Theory Techniques) Chapter between 27th
in his presentation traced the evolution of Microelectronics
technology, the role played by the three laws of Moore,
Shannon and Gene in accelerating the pace of microelectronic
developments, how the SOC trends have shaped the applications
driving SOC, the markets, SOC design approaches, SOC
technologies, Very Deep Submicron issues, verification and
testability issues, role of Intellectual Properties (IPs), and
whether SOC is a dream or reality for the country to address.
The talk had sketched a road map that could be taken to
succeed in the area. In the session that followed a live video
lecture on ‘Design flow for IP integration’ was given
through Internet by Mr.Grant Martin, Cadence Systems,
The fourth presentation on ‘Smart sensors and SOC’, by Dr.K.Neelakandan, Ether-Act software Laboratories, Bangalore and Visiting Professor at SASTRA covered the advances in semiconductor technology which makes SOC a reality, developments in sensor technology and traded the development of smart, integrated sensors and role of SOC in smart sensors. Newer developments like network enabled sensors, the IEEE 1491 standards and emerging trends of wireless enabled sensors were also touched.
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