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National Seminar on System on Chip (NSSOC - 2003)

27th Nov. to 29th Nov 2003 - A Report

 

A three-day national seminar on System-On-Chip was organized by TIFAC-CORE, SASTRA in association with Ministry of Information Technology, Govt. of India and IEEE India (Electron Devices Society / Microwave Theory Techniques) Chapter between 27th and 29th November 2003 . 85 delegates attended the seminar from academia and industry. The seminar was inaugurated by Dr.K.S.Chari, Chairman IEEE Electron Devices Society and Senior Director and Head, Microelectronics Division, Ministry of IT, Government of India.

 

HIGHLIGHTS

Dr.Chari in his presentation traced the evolution of Microelectronics technology, the role played by the three laws of Moore, Shannon and Gene in accelerating the pace of microelectronic developments, how the SOC trends have shaped the applications driving SOC, the markets, SOC design approaches, SOC technologies, Very Deep Submicron issues, verification and testability issues, role of Intellectual Properties (IPs), and whether SOC is a dream or reality for the country to address. The talk had sketched a road map that could be taken to succeed in the area. In the session that followed a live video lecture on ‘Design flow for IP integration’ was given through Internet by Mr.Grant Martin, Cadence Systems, USA . He discussed SoC design flow and methodologies, depending upon the characteristics both of IP and the end product. The concept of the reusability of an algorithmic IP approach at a system level, integration of IP on different levels, ranking from hardware layouts of digital, analog or mixed signal course, through the re-synthesis of RTL designs. He showed the trends to the single-pass ASIC design, block based integration of IP and the application oriented platform based design. The role of IP integration and verification was highlighted. The session ended with an interactive question answer session about the design constraints needed for system in package and System on Chip. The third major talk on ‘Moving India up the Semiconductor value chain’, by Shri. C.S.Balasubramanian, General Manager, Insilica Semi-conductors India Pvt. Ltd., Bangalore stressed the need for developing the design methodologies to satisfy the time-to-market consideration and the current scenario of the Indian VLSI companies. He talked about the strengths and various challenging issues. He also focused attention on other countries like Taiwan and China ’s technological aspects as well. A brief survey on what the Insilica is doing in VLSI era and how Insilica is going to compete with the SOC and manufacturing services was given. The session ended with the discussion on the need of industry experts to be always associated with the universities and institutions.

 

The fourth presentation on ‘Smart sensors and SOC’, by Dr.K.Neelakandan, Ether-Act software Laboratories, Bangalore and Visiting Professor at SASTRA covered the advances in semiconductor technology which makes SOC a reality, developments in sensor technology and traded the development of smart, integrated sensors and role of SOC in smart sensors. Newer developments like network enabled sensors, the IEEE 1491 standards and emerging trends of wireless enabled sensors were also touched.

 

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